1. Field of the Invention
The present invention relates to a microprogram control system and particularly to a microprogram control system in a data processing unit of a pipeline control system where the processing for reading a desired microinstruction is conducted at a high speed even when executing an instruction having a suboperation code.
2. Description of the Related Art
As shown in FIG. 1, for example, a prefetched instruction is executed by a pipeline processing unit having respective stages D, A, T, B, E and W. In FIG. 1, 1 is an instruction word or instruction register; 2 is a control memory or storage storing microinstructions; 3 to 7 are microinstruction field registers providing instructions or control signals to the hardware of stages D to W, 8 is a general purpose register group; 9 is a base register; 10 is an index register; 11 is a displacement register; 12 is an address calculating part or three input adder; 13 is a logical address register; 14 is TLB (address translation buffer); 15 is an address buffer; 16 is a buffer memory; 17 is an operand register; 18 to 20 are operand buffer registers; 21 is an operand register; 22 is an operation unit; and 23 is a result register The general purpose register group 8 is the same register group used in the three timings of D, B and W.
When an instruction 1 is supplied to the pipeline shown in FIG. 1, the microinstruction required for executing the relevant instruction 1 is read from control memory 2 in the stage D (decode) and loaded into the register 3 and values are loaded into the registers 9, 10, 11 in order to calculate the address of the operand (operand 2 in the figure) which is required for execution of the relevant instruction 1. The address of the operand is calculated by the calculation part 12 in the stage A (address) and the address is then loaded into the logic address register 13. The TLB 14 and buffer memory 16 are indexed through the stages T (translate) and B (buffer access) and a value for the operand 2 is loaded into the register 17. At this time, a value of operand 1 is also loaded into the register 21. From this state, the specified operation is carried out by the operation unit 22 in the stage E (execute) and the relevant operation result is loaded into the general purpose register 8 in the stage W (write).
Pipeline control is carried out as explained above, however, the processing corresponding to the respective stages is continued in such a form including reading the microinstruction from the control memory 2 (indicated in the figure) and executing it. Instructions are executed by the processing in the pipeline processing portion.
With the recent increase in the amount of data to be processed and diversification in the kinds of data processing performed, the requirement for enhancement of functions is increasing and, as a result, the number of different instructions executed by a pipeline processor also tend to increase. As a result, pipeline instructions having suboperation codes are increasing and the processing time necessary for reading the desired microinstruction corresponding to the instructions having the relevant suboperation code becomes a problem. Namely, it is a problem to coordinate the many processes by the pipeline processing portion. Moreover, in the data processing unit having suboperations, a single microprogram storage means (control memory 2) is provided with a field for storing branching data corresponding to the suboperation code. The control memory is accessed by the ordinary operation code and when it is sensed that the instruction has a suboperation code by means of the data read above, the control memory is accessed again by the suboperation code and the heading address of a microprogram for the instruction is obtained based on the data read as a result of the access. The access to control memory is carried out sequentially and, as a result, excessive control memory access operations are required.
This problem can be solved by using an address in the suboperation instructions having a length which includes the entire operation code and suboperation code as well as using such a length for the instructions having no suboperation code as the address for the first access to the control memory. However, in such a case, the needed capacity of the control memory increases until it is not practical.